1. Field of the Invention
The present invention refers to a processor with several calculating units and particularly to a processor with several calculating units, which can cooperate in a selectable mode of operation according to the dual rail logic.
2. Description of the Prior Art
Microprocessors and controllers, respectively, for chip card applications and other cryptographical applications often have to meet special security conditions. One of the main requirements is the security of the microprocessor against unauthorized reading out of secret information, particularly via side channel attacks. Side channel attacks occur, for example, by detecting the power consumption of a processor or by an electromagnetic or electrostatic detection of signal flows, wherein conclusions can be drawn about internal operations in the processor from the information obtained in that way. Apart from high-security tasks, a chip card controller also has to perform a plurality of conventional operations, where high performance is a big advantage and can result in an important market advantage. Examples would be applications in the mobile radio area, where the actual authentication only accounts for a very small part of the program run time. Still, for this a small portion, the full security of the authentication is required. Similarly, this holds true for electronic purses, even for the cash card, because in these applications, large parts of the program flow are also hardly security-critical, but the actual authentication however, is a high security task.
A highly secure execution of the processor kernel is, for example, possible in the so-called dual rail logic with precharge. The execution of a security microprocessor in dual rail logic with precharge is an important measure against side channel attacks, which are a big threat nowadays. However, it causes an economically disadvantageous larger area requirement in comparison to a prior art processor, and can lead to power penalties of the microprocessor due to the necessity of several clock phases. As a result, there will be a lower computing power and a lower data throughput, respectively, as well as an increased power consumption of the processor in comparison to standard architectures.